Verification Engineer :: Remote :: Contract

Hi,

Hope you are doing well,

Please find the job description given below and let me know your interest.

Position:Verification Engineer

Location:Remote

Duration:6+ month Contract

:

DESCRIPTION

RESPONSIBILITIES

The senior verifier will be called upon to:

·VHDL test benches for the verification of ASICs or FPGAs;

·apply the various techniques and approaches of the Universal Verification Methodology (UVM);

·contribute to the development of the test infrastructure;

·document and report problems found to designers and assist them in identifying the source of the problems;

·support laboratory testing.

QUALIFICATIONS

·Experience in writing test benches in SystemVerilog.

·Knowledge of VHDL sufficient to navigate through an existing design.

·Knowledge of UVM validation environments.

·Knowledge of Mentor Graphics' QuestaSim digital simulator.

·Knowledge of the Linux environment, scripting languages (Shell, Tcl, Python, "makefile").

·Familiarity with testbed automation techniques (Jenkins)

·Knowledge of source code management techniques (SVN, GIT).

·Bachelor's degree in electrical engineering, computer engineering or equivalent.

·10 and more years of experience in digital verification.

·Good interpersonal communication and teamwork skills.

·Good oral and written communication skills in French and English.

·Familiarity with Agile and Jira development methods.

·Multitasking ability.

Thanks & Regards,

Raveena Mourya

Email:[email protected]| Phone :972-325-9476/Extn.112

Linked In:linkedin.com/in/raveena-mourya-766314250

DMS Vision, INC

4645 Avon Lane, Suite 210

Frisco, TX 75033

http://dmsvisions.com/

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