Design Verification Engineer Jobs

Qualifications:

• Proficiency in System Verilog, Object Oriented Programming, Scripting Languages
• Experience in debugging designs of IP level (Wi-Fi Baseband, and MAC) or SOC level
• Detailed understanding of UVM methodology, flows and test-bench structures
• MS or higher degree in EE, CS or related fields,
• Entry level positions: 0-2 years of experience
• Good communication and documentation skills
• Experience in UVM development
• Senior and above level positions: a minimum of 2 years of experience
• Basic understanding of IEEE802.11 PHY and MAC standard
• Experience requirements:

Responsibilities:

• Create IP and system verification coverage plans, and generate test cases, based on the specification and review the plan with system architects and design engineers
• Conduct verification regressions, analyze the results, and review with design teams
• Architect and buildIP and system UVM verification environments.
• Report failures, participate in the debugging with various teams, and track bugs
• Develop verification flows for code coverage and functional coverage for Baseband, MAC, and SOC
• Work with system architects, algorithm engineers, and RTL designers to define Wi-Fi AP chip verification requirements.