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Company | Tara Technical Solutions (TTS) |
Address | San Francisco Bay Area, United States |
Employment type | FULL_TIME |
Salary | |
Expires | 2023-06-19 |
Posted at | 11 months ago |
Principal OR Senior Asic Verification with Emulation: Full-Time Direct Hire with Fortune 500 client.
San Francisco OR San Diego OR Irvine Locations:
In-Office locations are San Jose/Irvine/San Diego:
The position entails working closely with core designers, chip-level integration architects, software developers, and other verification engineers on state of the art broadband video products.
The team member would be contributing to the verification of highly advanced digital designs and extremely complex SOCs.
The candidate will be creating various emulation databases for complicated testing systems, developing both C/C++ tools and UVM UVCs, and writing scripts to support flows and debugging platforms. Experience with C/C++ is required, while knowledge of UVM and a scripting language such as PERL or Python is strongly desired. The colleague should have 8+PLUS PLUS years of design verification experience and 3+ years of emulation experience, preferably with Siemen’s Veloce platform.
*Position is on site at Irvine, San Jose, San Diego, or Singapore locations.
Required:
BSEE Verification Experience (8-12+ years PLUS)
Emulation Experience (3 years minimum )
C/C++ Experience Verilog or VHDL Knowledge
Strong debugging skills:
Strongly desired: NOT a MUST HAVE.
UVM Knowledge
Scripting Knowledge
RTL Design Experience.
Reach out for more information in confidence :
San Francisco OR San Diego OR Irvine Locations:
In-Office locations are San Jose/Irvine/San Diego:
The position entails working closely with core designers, chip-level integration architects, software developers, and other verification engineers on state of the art broadband video products.
The team member would be contributing to the verification of highly advanced digital designs and extremely complex SOCs.
The candidate will be creating various emulation databases for complicated testing systems, developing both C/C++ tools and UVM UVCs, and writing scripts to support flows and debugging platforms. Experience with C/C++ is required, while knowledge of UVM and a scripting language such as PERL or Python is strongly desired. The colleague should have 8+PLUS PLUS years of design verification experience and 3+ years of emulation experience, preferably with Siemen’s Veloce platform.
*Position is on site at Irvine, San Jose, San Diego, or Singapore locations.
Required:
BSEE Verification Experience (8-12+ years PLUS)
Emulation Experience (3 years minimum )
C/C++ Experience Verilog or VHDL Knowledge
Strong debugging skills:
Strongly desired: NOT a MUST HAVE.
UVM Knowledge
Scripting Knowledge
RTL Design Experience.
Reach out for more information in confidence :
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