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Package Design Engineer Jobs

Company

Broadcom
Address , San Jose, Ca
Employment type FULL_TIME
Salary $126,000 - $210,000 a year
Expires 2023-07-29
Posted at 11 months ago
Job Description
Please Note:
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:
Work with business units marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability.
  • Manage IC packaging activity from concept through development, qualification through high volume production
  • Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on packaging issues
  • Support NPI bring-up, package qualification, and sustain support in production + multi-source activities for capacity, cost, & manufacturing flexibility needs
  • Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages using Cadence APD for FCBGA, WLBGA & WLCSP products
  • Create package design documentation and assembly instructions
  • Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new technology/structure development etc.)
  • Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution
  • Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
  • Ensure designed packages meet CPI, SI/PI, and thermal requirements of silicon products
  • Interface with other operations functional groups such as product engineering, foundry, test, and QA
  • Work close with QA and customers to resolve quality issues
Job Requirements
  • Hands-on expertise of assembly processes for flipchip, MCM, WLBGA and WLCSP packages for advanced node silicon products (16nm, 7nm, 5nm and beyond)
  • Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.
  • Good understanding of materials as related to Chip Packaging Interaction (CPI)
  • Strong authority on Cadence APD for custom substrate design
  • Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)
  • Experience : Bachelors and 12+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience
Additional :
Compensation and Benefits
The annual base salary range for this position is $126,000 - $210,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.